1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to test structures and a method of determining the complete location of a buried short using voltage contrast inspection.
2. Background Art
In-line voltage contrast (VC) inspection is a powerful technique for detecting and isolating yield limiting defects in the semiconductor fabricating industry. In-line VC inspection includes scanning the wafer surface in which test structures exist with a scanning electron microscope (SEM). As the inspection proceeds, the SEM induces charge on all electrically floating elements whereas any grounded elements remain at zero potential. This potential difference is visible to the SEM. In particular, for electron landing energies less than the second crossover of the secondary electron yield curve (approximately 1.5 keV for tungsten (W) and copper (Cu)), grounded elements appear bright whereas floating elements appear dark.
Test structures exploiting this phenomenon can be created for many yield limiting defects including metal, gate and active region shorts and opens, and via and contact opens. For example, FIGS. 1A-B, show a short (FIG. 1B) indicated by a normally floating (dark) element becoming bright, and an open (FIG. 1A) indicated when a normally bright element becomes dark.
One advantage of this technique is that even if the defect causing the electrical failure is buried or extremely small, its existence is flagged by a change in the VC inspection signal of the entire element. Referring to FIG. 2, as a result of this situation it is possible to scan (between dashed lines) just the bottom of a test structure 10 and still detect the existence of an electrically active defect 12, 14 anywhere on that structure. See, for example, Weiner, K., Henry T., Satya, A., Verman, G., Wu, R., Patterson, O., Crevasse, B., Cauffman, K., Cauffman, W., Defect Management for 300 mm and 130 mm Technologies Part 3: Another Day, Another Yield Learning Cycle, Yield Management Solutions magazine, Vol. 4, Iss. 1, pp. 15-27, Winter 2002. This technique is referred to as “area acceleration” because only a small portion of an area (between dashed lines) must be scanned during VC inspection in order to identify a defect. FIG. 2 shows how the VC inspection pattern changes when a short 12 or open 14 exists. Test structure 10 includes a grounded comb 16 including grounded tines 18 which are interleaved with ungrounded tines 20 of a second backless comb 22. Ungrounded tines 22 are isolated from each other and grounded comb 16. If an open 14 exists on a grounded tine 180 of grounded comb 16, the VC signal changes on that tine 180, e.g., it is darker in parts than other grounded tines 18 on the open portion. If a short 12 exists between a grounded tine 18 and a floating, ungrounded tine 20S of backless comb 22, the VC signal of the floating tine changes, e.g., the shorted ungrounded tine 20S illuminates brighter than other ungrounded tines 20.
KLA-Tencor markets a product called uLoop™ that is based on the above-described principal. Using this technology, once a defect is detected using a scan as shown in FIG. 2 (between dashed lines) in a first (x) direction, the x coordinate of the defect is established. Next, the structure can be scanned in a second (y) direction for the location of the buried short to be determined. The uLoop™ software does this automatically. It also can be done manually fairly easily, although not nearly as quickly, using an inspection SEM, a review or critical dimension (CD) SEM or a focused ion beam (FIB) tool. In any case, only a small fraction of the test structure needs to be scanned. Applying area acceleration typically results in a time savings of 70-90%.
Unfortunately, in some cases a defect is not visible. For example, oftentimes contact or via opens, buried metal shorts, gate oxide shorts or silicide pipes are not visible. Such defects are often referred to as buried shorts. The location of buried opens, and in particular their y coordinate, on area accelerated test structures can be determined because the VC signal will change at the location of the defect as shown in FIG. 2 for tine 180, and as shown in the images of FIGS. 1A and 1C. The location cannot, however, be established for buried shorts because the illumination brightness of the tine containing the short will be the same regardless of the short's location. For example, shorted tine 20S in FIG. 2 illuminates the same along it's entire length. FIG. 1B also shows this situation.
One approach for isolating a buried short using VC inspection is to divide the test structure design into small pieces for analysis. FIG. 3 shows how test structure 10 in FIG. 2 may be modified so that a buried short could be isolated. FIG. 4 shows such a test structure 30 that could be used to detect silicide pipes, with polysilicon conductor regions 31 and source and drain regions 33. Unfortunately, area accelerated VC inspection cannot be applied to these structures. That is, the entire structure must be VC inspected. In another approach, an area accelerated test structure is used like test structure 10 in FIG. 2, and the defect is located using an in-line FIB tool. This approach requires that the defective tine be cut in half. The half with the VC signal would then be split again and so forth. A buried short on a 1 mm long tine could be isolated to a 1 μm segment using 10 cuts. Unfortunately, this approach is expensive and time consuming and results in wafer scrap.
In view of the foregoing, there is a need in the art for a solution to the problems of the related art.